The invention relates to a method for the fabrication of an integrated semiconductor component.
Integrated semiconductor components are fabricated by forming integrated circuits on semiconductor wafers. The integrated circuits are conductively connected internally and externally to the semiconductor wafer, with the result that structured conductive layers are formed, which in turn are separated from one another by dielectric layers. To ensure that the components are able to function perfectly, the individual active elements of the integrated circuits have to be isolated from one another. This is achieved by what are known as isolation trenches which are formed in the semiconductor wafer and are then filled with a nonconductive material to form what is known as a shallow trench isolation or STI. Hitherto, the step of filling with nonconductive material has usually been carried out by conformal deposition of an isolation layer, i.e. by deposition of isolation material at the same rate overall the accessible surfaces. As a result, a layer of uniform thickness is formed on the semiconductor component.
In recent years, the complexity of integrated circuits has increased considerably, while at the same time the size of the circuits has decreased drastically. For this reason, the isolation trenches which are required in order to separate the individual active elements have been formed with an increasingly great aspect ratio. However, conventional conformal deposition processes can no longer be used to fill these isolation trenches with a high aspect ratio, since the deposition of isolation material on the walls of the isolation trench closes off the trench before it has been completely filled. The cavities which are formed in this way prevent optimum isolation properties from being achieved.
With increasing complexity for new technological shrinks and the associated increasing aspect ratio of the isolation trenches, therefore, nonconformal filling processes have become increasingly important for filling the isolation trenches. In these nonconformal filling processes, isolation material is deposited at different rates on different surfaces of the semiconductor component, with the result that isolation layers of different thicknesses are deposited on the semiconductor component. Since the isolation material is deposited more quickly at the bottom of the isolation trenches than on the walls of the trenches, the isolation trenches are filled with the isolation material without cavities being formed. The remaining structures of the semiconductor component are likewise covered by an isolation layer (see FIG. 1).
When using these nonconformal filling processes, the problem arises that there is no sealing of the wafer back surface. However, if there is no back surface seal, there is a risk that, during subsequent thermal processes, materials, such as for example dopants, will escape from the back surface of the wafer and will be deposited on the adjoining wafer, since the wafers are usually subjected to the thermal processes while they are standing in pits. This may affect further process steps and also the electrical functionality of the integrated circuit. In particular, the threshold voltage, leakage currents and GOX (gate oxide regions) reliability are problem sources which need to be mentioned.